Application specific integrated circuits
Application specific integrated circuits, or ASICs are integrated circuits (ICs) designed to suit requirements that are specific to a particular system or application. ASICs differ from ICs in that the latter may be designed to suit several general requirements. For example, a chip designed to control the temperature of an oven or one designed to control a television remotely is an ASIC, whereas a memory chip used in your home computer is an IC.
Application specific integrated circuits are categorized according to the technology used for manufacturing them. These types are semi-custom ASICs, full custom ASICs, Gate Array (GA) type or standard cell based ICs(CBICs), (field programmable gate arrays(FPGA), and System-on-a-chip(SoCs).
Full-custom Application specific integrated circuits are those which do not make use of pre-tested and pre-characterized cells for all or part of the design. In other words, all the logic cells, circuits, or layout of a full-custom ASIC are designed specifically for one ASIC. A full-custom approach to ASIC design is followed only if there are no suitable existing cell libraries available for the entire design. Sometimes, the approach is also chosen because existing cell libraries are not fast enough, or the logic cells are not small enough, or consume too much power. Full-custom design is also used in case the ASIC technology is new or very specialized. The trend of using the full-custom IC design approach is decreasing because of the problems encountered during the design.
Cell-based ASICs (CBICs) make use of pre-designed,
pre-tested, and pre-characterized logic cells such as AND gates, OR gates, multiplexers, and flip-flops for the design. These predefined cells are also referred to as standard cells. The standard-cell areas (also called flexible blocks) in a CBIC are built of rows of standard cells similar to a wall built of bricks.
The standard-cell areas may be used in combination with larger pre-designed cells, known as megacells. Megacells are also known as mega-functions, full-custom blocks, system-level macros (SLMs), fixed blocks, cores, or Functional Standard Blocks (FSBs). Examples of such megacells are microcontrollers and microprocessors.
The ASIC designer needs to define only the placement of the standard cells and the interconnect in a CBIC.
The CBIC approach for ASIC fabrication saves time and money, reduces risk, and allows each standard cell to be optimized individually. For example, during the cell-library design, the designer can choose each transistor in a standard cell to maximize speed or minimize area. The drawbacks of this approach are the time and expense of designing or buying the standard-cell library and the time needed to fabricate all layers of the ASIC for each new design.
The gate array (GA) or gate-arraybased Application specific integrated circuits is another type of ASIC which uses a predefined pattern of transistors on a silicon wafer. The pre-defined pattern of transistors on a gate array is the base array, and the smallest element that is replicated to make the base array (like tiles on a floor) is the base cell (sometimes called a primitive cell).
Only the top few layers of metal, which define the interconnect between transistors, are defined by the designer using custom masks. To distinguish this type of gate array from other types of gate array, it is often called a masked gate array (MGA). The designer chooses from a gate-array library of pre-designed and pre-characterized logic cells. The logic cells in a gate-array library are often called macros.
The Channel-free gate array, sea-of-gates array, or SOG array is another important type of ASIC. In this type of MGA, only some (the top few) mask layers comprising the interconnect are customized. The manufacturing lead time for such ASICs is between two days and two weeks.
The key difference between a channel-less gate array and channeled gate array is that there are no pre-defined areas set aside for routing between cells on a channel-less gate array. In addition, channel-less gate arrays have higher logic density than channeled gate arrays. (Logic density is the amount of logic that can be implemented in a given silicon area.)
Using wafers prefabricated up to the metallization steps reduces the time needed to make an MGA, the turnaround time, to a few days or at most a couple of weeks. The costs for all the initial fabrication steps for an MGA are shared for each customer and this reduces the cost of an MGA compared to a full-custom or standard-cell ASIC design.
There are the following different types of MGA or gate-arraybased ASICs:
Channeled gate arrays-Only the interconnect is customized. The interconnect uses predefined spaces between rows of base cells. Manufacturing lead time is between two days and two weeks.
The Manufacturing lead time of Channel-less gate arrays is between two days and two weeks.. -Only some (the top few) mask layers are customizedthe interconnect.
Structured gate arrays combine some of the features of CBICs and MGAs.
Another category of ASIC, Programmable logic devices ( PLDs ) are standard ICs that are available in standard configurations from a catalog of parts and are sold in very high volume to many different customers. You can configure a PLD to meet the needs of a specific application, and hence, it also belongs to the family of ASICs. PLDs use different technologies to allow programming of the device. They generally have a single large block of programmable interconnect and a matrix of logic macrocells that consists of programmable array logic followed by a flip-flop or latch. A PLD uses no customized mask layers or logic cells, and has fast design turnaround. A particular category of ASIC, which includes large building blocks such as ROM, EPROM or 32 bit processor is referred to as a System-on-a-Chip (SoC).
Generally, the top-down hierarchical approach is followed for the ASIC design process, and consists of a sequence of well-defined steps related to each other. The steps include defining the functions to be designed; organizing the circuit blocks that implement these logic functions within the area of the IC; verification and simulation at several stages of design (e.g., behavioral simulation, gate-level simulation, circuit simulation; routing of physical interconnections among the blocks, and finally the detailed placement and transistor-level layout of the VLSI circuit. The top-down hierarchical approach for ASIC design is used to design one of the blocks comprising the overall IC, representing a circuit block in terms of simpler blocks.
Over the years, there has been rapid advancement in the technology used for manufacturing ASICs as a result of which the functionality available in the chip has grown manifold. The development of EDA (electronic design automation) and CAD (computer aided design) tools have contributed to the advancements in ASIC design and have made complex microelectronics technologies available to system designers. A look at the statistics of ASIC evolution over the past decade shows that ASICs have shown considerable improvement in ASIC gates per chip, number of logic levels, on-chip speed, chip size, DRAM/chip, and number of I/O ports. Simultaneously, the chips have reduced in size (measured in microns) from 0.35 micron to about .10micron, and a considerable decrease in supply voltage requirement is also observed.
In making a choice between the different ASIC types ASIC companies make use of spreadsheet models to calculate their costs. At present, there are several ASIC manufacturing companies around the world; the prominent ones include ST Microelectronics, IBM, LSI Logic, SMIC, Texas Instruments, Agere, Fujitsu, and X Fab.
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